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Tuesday, July 7th 2026

Intel "Nova Lake" to Feature AVX-512 on Both P-cores and E-cores

by
btarunr
 Discuss (84 Comments)
Intel's next-generation Core Ultra Series 4 "Nova Lake" processors will mark an official return of AVX-512 to the company's client processor lineup. The 512-bit SIMD instruction set will be featured on both the "Coyote Cove" P-cores, and "Arctic Wolf" E-cores, according to Jay Kihn. It is a requirement for both core types to feature an identical ISA, without which thread migration between the two core types will result in runtime errors arising from ISA mismatch.

The last Core processor to feature an official implementation of AVX-512 was 11th Gen Core "Rocket Lake," in which AVX-512 workloads would notoriously cause the 14 nm processor to overheat. Intel would deprecate AVX-512 on all succeeding client microarchitectures, mainly because their respective E-core types didn't support it. Intel is expected to offer a client-relevant set of AVX-512 instructions. Meanwhile, AMD introduced AVX-512 support with "Zen 4," and would go on to improve AVX-512 performance with "Zen 5." The reentry of AVX-512 on Core could advance client AI inferencing applications.
Source: JayKihn (Twitter)

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84 Comments on Intel "Nova Lake" to Feature AVX-512 on Both P-cores and E-cores

#1
Sol_Badguy
@_roman_

Bro you got your wish, AVX-512 instructions.

Ready to upgrade? :laugh:
Posted on Reply
#2
ncrs
This was known since May 2025 when Intel changed AVX10's specification by removing 256bit-only core options:
Remove AVX10/256-specific architectural features (VMX extensions, YMM embedded rounding support, and em- phasis on VL-specific enumerations). AVX10/512 will be used in all Intel® products, supporting vector lengths of 128, 256, and 512 in all product lines.
Or rather since Nova Lake was confirmed to feature AVX10. AVX10 is fully backwards compatible with most of AVX-512 (it's missing deprecated Xeon Phi parts) so we get AVX-512 on E-cores, but in fact we get much more with AVX10 and APX.
Posted on Reply
#3
lemonadesoda
Glad to hear the overheating problem has been solved. It is just as fast as before, or do they throw NOPs to add microdelays.
Posted on Reply
#4
iameatingjam
Sure am glad rpcs3 will get a boost.

Seriously though, I wonder if this is evidence that ecores will become the new pcores eventually. Or if it was just a bad look to not have it all this time so intel found a way.
Posted on Reply
#5
dj-electric
iameatingjamSure am glad rpcs3 will get a boost.

Seriously though, I wonder if this is evidence that ecores will become the new pcores eventually. Or if it was just a bad look to not have it all this time so intel found a way.
E cores might become P cores, but... P cores will also become E cores.

This will be a great riddle that will be solved in the future, can't wait. :)
Posted on Reply
#6
Grimling
Is there any practical use of the AVX-512 other than ycruncher?
Posted on Reply
#7
qcmadness
Getting 256-bit / 512-bit FPUs is not free.
Posted on Reply
#9
melkor_unlimited
dj-electricE cores might become P cores, but... P cores will also become E cores.

This will be a great riddle that will be solved in the future, can't wait. :)
Matthew 20:16
So the last shall be first, and the first last.
For many be called, but few chosen.
GrimlingIs there any practical use of the AVX-512 other than ycruncher?
For the mere mortals?
The above mentioned RPCS3
and some video encoding routines.

And some AI stuff for those who are into it and do not want to pay thousands $$$ for GPU.
Posted on Reply
#10
ebivan
...until Intel decides to deactivate them again with some microcode update at any point in the future...
Posted on Reply
#11
XeonsNOpterons
This was already pretty much known. AVX10.2 includes AVX-512, so yeah, nothing really new. This will only smash Zen 6 likely even more as the E-cores will get much faster still.
GrimlingIs there any practical use of the AVX-512 other than ycruncher?
Plenty, if developers actually coded for using it. It is far more energy efficient than AVX2 and SSE4.2. It is a common misconception that it is more power hungry, but that is only if you run the same clock speeds. AVX-512 can output more calculations even at lower clock speeds while maintaining the same power draw.

There are legitimate difficulties with coding for AVX-512 as you need to essentially have your calculations lined up neatly so they can feed into the wider bus of AVX-512. Otherwise, you are just not taking advatange of the larger throughput. But, unfortunately, part of the reason developers do not code for it is laziness and the misconception it is more power hungry for their calculations. Maybe now that both Intel and AMD mainstream CPUs support AVX-512 they will forgo their laziness.
Posted on Reply
#12
BoxCutter
GrimlingIs there any practical use of the AVX-512 other than ycruncher?
I think compilers take advantage of that, which def matters.
Posted on Reply
#13
_Under2World_
ebivan...until Intel decides to deactivate them again with some microcode update at any point in the future...
Have they done it in the past ?
afik they only stopped providing the option inside new products and didn't disabled it from a product they already lauched
Posted on Reply
#14
igormp
I wonder if it'll be double pumped with 256-bit units (like Zen 4/Zen 5 mobile), or if there will be actual 512-bit units (like in Zen 5 desktop/server), and how many units each of those chips will have. IIRC the HEDT/Server offerings from Intel had 2 512-bit FMA units per core, whereas the consumer parts only had 1 units.

There's also the option of the E-cores using 256-bit units (or even 128-bit ones!) + double/quad-pumping, while the P-cores have full blown 512-bit units.
Posted on Reply
#15
user556
100% identical ISA between core types - AMD finally getting some competition ... sometime in the future.
Posted on Reply
#16
qcmadness
igormpI wonder if it'll be double pumped with 256-bit units (like Zen 4/Zen 5 mobile), or if there will be actual 512-bit units (like in Zen 5 desktop/server), and how many units each of those chips will have. IIRC the HEDT/Server offerings from Intel had 2 512-bit FMA units per core, whereas the consumer parts only had 1 units.

There's also the option of the E-cores using 256-bit units (or even 128-bit ones!) + double/quad-pumping, while the P-cores have full blown 512-bit units.
I would expect e-cores to have 2-3 256-bit FPUs while p-cores to have 1-2 512-bit FPUs.
Posted on Reply
#17
XeonsNOpterons
igormpI wonder if it'll be double pumped with 256-bit units (like Zen 4/Zen 5 mobile), or if there will be actual 512-bit units (like in Zen 5 desktop/server), and how many units each of those chips will have. IIRC the HEDT/Server offerings from Intel had 2 512-bit FMA units per core, whereas the consumer parts only had 1 units.

There's also the option of the E-cores using 256-bit units (or even 128-bit ones!) + double/quad-pumping, while the P-cores have full blown 512-bit units.
I have a feeling, considering I think only AMD did the double-pumped scheme for AVX-512 in Zen 4, that Intel will have full 512 FMA units in both cores like they always have, but the E-cores may only have on 512-bit FMA unit while the P-cores will have two like standard.
Posted on Reply
#18
bug
I remember first AVX-512 implementations were panned for being just power hungry for little in return. And we get AVX-512 on E-cores. That's some development.
Posted on Reply
#19
XeonsNOpterons
bugI remember first AVX-512 implementations were panned for being just power hungry for little in return. And we get AVX-512 on E-cores. That's some development.
Again, they were power-hungry at the same clock speeds, but still delivered more throughput at the same power consumption. Also, at least in my experience with Redwood Cove cores, Intel has made the power draw increase from running AVX-512 much less.
Posted on Reply
#20
qcmadness
bugI remember first AVX-512 implementations were panned for being just power hungry for little in return. And we get AVX-512 on E-cores. That's some development.
Yes, but at what expense?
Posted on Reply
#21
bug
qcmadnessYes, but at what expense?
I don't get that. Do you want me to predict the price? I'm pretty sure not even Intel knows that, at this point.
Posted on Reply
#22
qcmadness
bugI don't get that. Do you want me to predict the price? I'm pretty sure not even Intel knows that, at this point.
I mean, expanding the FPUs to 256-bit / 512-bit requires die size.

If you compare Zen 5 and Zen 5 Lite (256-bit FPU version found in APU), substantial transistor budget is given to the beefier FPUs.
Posted on Reply
#23
bug
qcmadnessI mean, expanding the FPUs to 256-bit / 512-bit requires die size.

If you compare Zen 5 and Zen 5 Lite (256-bit FPU version found in APU), substantial transistor budget is given to the beefier FPUs.
Yeah, well, it's engineering. Any decision you make, comes with downsides. All it matters is you get something better overall at the end of it.
Posted on Reply
#24
N/A
I could shave off 1-2 minutes in realityscan but no amount of free gifts can overcome the prohibitive DDR5 tax.
Posted on Reply
#25
Tek-Check
iameatingjamSure am glad rpcs3 will get a boost.

Seriously though, I wonder if this is evidence that ecores will become the new pcores eventually. Or if it was just a bad look to not have it all this time so intel found a way.
They are working on unified core already. Most likely after Hammer Lake, post-1954 socket.
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